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| author | Richard Henderson <richard.henderson@linaro.org> | 2021-08-23 12:55:25 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-09-01 11:59:12 +1000 |
| commit | 6922eee6acc09720883653246daa16e7dc4e2d3c (patch) | |
| tree | 47ba36230c8424c767c70fe5ebf73d903a42de79 /python/qemu/utils/accel.py | |
| parent | cce762a75e2cd9d9f121949c68f04ab8fabcdd3a (diff) | |
| download | focaccia-qemu-6922eee6acc09720883653246daa16e7dc4e2d3c.tar.gz focaccia-qemu-6922eee6acc09720883653246daa16e7dc4e2d3c.zip | |
target/riscv: Use gen_shift_imm_fn for slli_uw
Always use tcg_gen_deposit_z_tl; the special case for shamt >= 32 is handled there. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-21-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'python/qemu/utils/accel.py')
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