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| author | Cameron Esfahani <dirty@apple.com> | 2021-10-28 18:33:15 -0700 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2022-03-15 13:36:33 +0100 |
| commit | 704afe34d8c4dbee3e88cfaa25c8561364169695 (patch) | |
| tree | 083273d82e426cfc9a8890df71183652ba296c2c /python/qemu/utils/accel.py | |
| parent | 004900acbcde82d52d80404dea7f43ce5f8b78fb (diff) | |
| download | focaccia-qemu-704afe34d8c4dbee3e88cfaa25c8561364169695.tar.gz focaccia-qemu-704afe34d8c4dbee3e88cfaa25c8561364169695.zip | |
hvf: Use standard CR0 and CR4 register definitions
No need to have our own definitions of these registers. Signed-off-by: Cameron Esfahani <dirty@apple.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'python/qemu/utils/accel.py')
0 files changed, 0 insertions, 0 deletions