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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-03-01 11:59:48 -1000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-03-02 19:27:37 +0000 |
| commit | 777ab8d84442dd6c0c5fbf787de87779d5ab82e8 (patch) | |
| tree | 5fd24e221ad8c56addbcc50e38a8f402eddee39f /python/qemu/utils/accel.py | |
| parent | f4ecc01537684a4125c35433f3097295d0a1f839 (diff) | |
| download | focaccia-qemu-777ab8d84442dd6c0c5fbf787de87779d5ab82e8.tar.gz focaccia-qemu-777ab8d84442dd6c0c5fbf787de87779d5ab82e8.zip | |
target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVA
The original A.a revision of the AArch64 ARM required that we force-extend the addresses in these registers from 49 bits. This language has been loosened via a combination of IMPLEMENTATION DEFINED and CONSTRAINTED UNPREDICTABLE to allow consideration of the entire aligned address. This means that we do not have to consider whether or not FEAT_LVA is enabled, and decide from which bit an address might need to be extended. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220301215958.157011-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'python/qemu/utils/accel.py')
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