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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-05-24 14:28:08 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-06-24 16:48:07 +0200 |
| commit | 85ccd962d622475e6281ea98ab69c03de7bc37c1 (patch) | |
| tree | 92b47b1232769e82b788612aa6f00a2f6f822216 /python/qemu/utils/accel.py | |
| parent | a9eb3b49fb2224ca2eda514b55c5d288379460ee (diff) | |
| download | focaccia-qemu-85ccd962d622475e6281ea98ab69c03de7bc37c1.tar.gz focaccia-qemu-85ccd962d622475e6281ea98ab69c03de7bc37c1.zip | |
target/mips: Restrict some system specific declarations to sysemu
Commit 043715d1e0f ("target/mips: Update ITU to utilize SAARI
and SAAR CP0 registers") declared itc_reconfigure() in public
namespace, while it is restricted to system emulation.
Similarly commit 5679479b9a1 ("target/mips: Move CP0 helpers
to sysemu/cp0.c") restricted cpu_mips_soft_irq() definition to
system emulation, but forgot to restrict its declaration.
To avoid polluting user-mode emulation with these declarations,
restrict them to sysemu. Also restrict the sysemu ITU/ITC/IRQ
fields from CPUMIPSState.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210617174323.2900831-6-f4bug@amsat.org>
Diffstat (limited to 'python/qemu/utils/accel.py')
0 files changed, 0 insertions, 0 deletions