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| author | Mark Corbin <mark@dibsco.co.uk> | 2024-09-17 01:51:03 +1000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-10-02 15:11:51 +1000 |
| commit | 9d49b1c9edf829e571093088ddff0b73db3110c6 (patch) | |
| tree | 5e9ecc0ed790535ab3ba29f07703dd55b2f20233 /python/qemu/utils/accel.py | |
| parent | 1165e30d950a41a2898f7ab426984cb0d0251f72 (diff) | |
| download | focaccia-qemu-9d49b1c9edf829e571093088ddff0b73db3110c6.tar.gz focaccia-qemu-9d49b1c9edf829e571093088ddff0b73db3110c6.zip | |
bsd-user: Implement RISC-V CPU initialization and main loop
Added the initial implementation for RISC-V CPU initialization and main loop. This includes setting up the general-purpose registers and program counter based on the provided target architecture definitions. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-2-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'python/qemu/utils/accel.py')
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