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| author | Luc Michel <luc.michel@amd.com> | 2025-09-26 09:07:36 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-10-07 10:35:36 +0100 |
| commit | aaf889ebdc6ed054a975465fee18feea2450c446 (patch) | |
| tree | 56b1147ae8420962c3809206ea161395088110ad /python/qemu/utils/accel.py | |
| parent | b913b3cb26d531f71ccf89e886c0d0f520e80077 (diff) | |
| download | focaccia-qemu-aaf889ebdc6ed054a975465fee18feea2450c446.tar.gz focaccia-qemu-aaf889ebdc6ed054a975465fee18feea2450c446.zip | |
hw/arm/xlnx-versal: crl: refactor creation
Refactor the CRL device creation using the VersalMap structure. The connections to the RPU CPUs are temporarily removed and will be reintroduced with next refactoring commits. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-19-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'python/qemu/utils/accel.py')
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