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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-06-17 13:15:54 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-06-21 17:12:50 +0100 |
| commit | ab59362fca0c23fbd21daceb78d6b2966fbf9793 (patch) | |
| tree | 02154d0f82e9f8b5a778763c3d83f4bb351b5cad /python/qemu/utils/accel.py | |
| parent | 614dd4f3ba2a025eae5235c3466ef6da191879f6 (diff) | |
| download | focaccia-qemu-ab59362fca0c23fbd21daceb78d6b2966fbf9793.tar.gz focaccia-qemu-ab59362fca0c23fbd21daceb78d6b2966fbf9793.zip | |
target/arm: Implement MVE VDUP
Implement the MVE VDUP insn, which duplicates a value from a general-purpose register into every lane of a vector register (subject to predication). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-11-peter.maydell@linaro.org
Diffstat (limited to 'python/qemu/utils/accel.py')
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