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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-06-17 13:16:01 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-06-21 17:12:51 +0100 |
| commit | abc48e310cc95f616ae65ccb167019eebf7e705b (patch) | |
| tree | 32c038f84ac1814b39d2c8b59010ec12377d8355 /python/qemu/utils/accel.py | |
| parent | bc67aa8d561e6ebf93b724c9abf3a7a1f95839c9 (diff) | |
| download | focaccia-qemu-abc48e310cc95f616ae65ccb167019eebf7e705b.tar.gz focaccia-qemu-abc48e310cc95f616ae65ccb167019eebf7e705b.zip | |
target/arm: Implement MVE VHADD, VHSUB
Implement MVE VHADD and VHSUB insns, which perform an addition or subtraction and then halve the result. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-18-peter.maydell@linaro.org
Diffstat (limited to 'python/qemu/utils/accel.py')
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