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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-06-17 13:16:09 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-06-24 14:58:47 +0100 |
| commit | b050543b68308427792cc024fb2905b041ebc253 (patch) | |
| tree | cdbd67375094453e49abec175d6e6e399fce11eb /python/qemu/utils/accel.py | |
| parent | 644f717c35ec29d53f6fc34523e096fbad6eeaf9 (diff) | |
| download | focaccia-qemu-b050543b68308427792cc024fb2905b041ebc253.tar.gz focaccia-qemu-b050543b68308427792cc024fb2905b041ebc253.zip | |
target/arm: Implement MVE VBRSR
Implement the MVE VBRSR insn, which reverses a specified number of bits in each element, setting the rest to zero. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-26-peter.maydell@linaro.org
Diffstat (limited to 'python/qemu/utils/accel.py')
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