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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-04-25 16:19:44 +0100 |
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| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-05-25 13:57:52 +0000 |
| commit | eda151599654e3981967052defd49945e7879596 (patch) | |
| tree | 7c3a0305ee58a6ad2a0369d4092cea0c1594e6bc /python/qemu/utils/accel.py | |
| parent | d1c3f4e9ed160505c10b3d2acccf43e70e799ed3 (diff) | |
| download | focaccia-qemu-eda151599654e3981967052defd49945e7879596.tar.gz focaccia-qemu-eda151599654e3981967052defd49945e7879596.zip | |
tcg/riscv: Use ADD.UW for guest address generation
The instruction is a combined zero-extend and add. Use it for exactly that. Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'python/qemu/utils/accel.py')
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