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| author | LIU Zhiwei <zhiwei_liu@c-sky.com> | 2021-05-21 13:48:16 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-06-08 09:59:43 +1000 |
| commit | eee2d61e202b5bd49a5eb211e347e02c86287ef4 (patch) | |
| tree | 70ba046ba1c0c24f4bbe313b25a31c8036f88363 /python/qemu/utils/accel.py | |
| parent | 787a4baf91fa2ff36b901c0b31ea73f3f0739415 (diff) | |
| download | focaccia-qemu-eee2d61e202b5bd49a5eb211e347e02c86287ef4.tar.gz focaccia-qemu-eee2d61e202b5bd49a5eb211e347e02c86287ef4.zip | |
target/riscv: Pass the same value to oprsz and maxsz.
Since commit e2e7168a214b0ed98dc357bba96816486a289762, if oprsz is still zero(as we don't use this field), simd_desc will trigger an assert. Besides, tcg_gen_gvec_*_ptr calls simd_desc in it's implementation. Here we pass the value to maxsz and oprsz to bypass the assert. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210521054816.1784297-1-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'python/qemu/utils/accel.py')
0 files changed, 0 insertions, 0 deletions