diff options
| author | Fabiano Rosas <farosas@linux.ibm.com> | 2022-01-28 13:15:05 +0100 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2022-01-28 13:15:05 +0100 |
| commit | f9911e1e5513ebf661ae871ae31269a9a1cfabdc (patch) | |
| tree | 831eadfe1d1dcc9ff9d9927b29d716fec91e9e9e /python/qemu/utils/accel.py | |
| parent | 4d8ac1d15ec34d0967c7e51e375e72c522c1e6b5 (diff) | |
| download | focaccia-qemu-f9911e1e5513ebf661ae871ae31269a9a1cfabdc.tar.gz focaccia-qemu-f9911e1e5513ebf661ae871ae31269a9a1cfabdc.zip | |
target/ppc: 405: Data Storage exception cleanup
The 405 has no DSISR or DAR, so convert the trace entry to
use ESR and DEAR instead.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg : - changed registers to ESR and DEAR.
- updated commit log ]
Message-Id: <20220118184448.852996-12-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'python/qemu/utils/accel.py')
0 files changed, 0 insertions, 0 deletions