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| author | eopXD <eop.chen@sifive.com> | 2022-05-05 02:42:17 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-05-24 09:48:20 +1000 |
| commit | 02b511985e33d71859943682860f629ead5bd20a (patch) | |
| tree | 51442a3b469355afd92d2abfc7d1fc093cb27c01 /python/qemu/utils/py.typed | |
| parent | d6cd3ae0ebdfab9922f932dc303e1faa618ea547 (diff) | |
| download | focaccia-qemu-02b511985e33d71859943682860f629ead5bd20a.tar.gz focaccia-qemu-02b511985e33d71859943682860f629ead5bd20a.zip | |
target/riscv: rvv: Fix early exit condition for whole register load/store
Vector whole register load instructions have EEW encoded in the opcode, so we shouldn't take SEW here. Vector whole register store instructions are always EEW=8. Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165181414065.18540.14828125053334599921-0@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'python/qemu/utils/py.typed')
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