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authorEric Auger <eric.auger@redhat.com>2025-07-01 15:08:26 +0100
committerPeter Maydell <peter.maydell@linaro.org>2025-07-01 15:08:26 +0100
commita2e3508ac0f2aeb27f859362bf8e6dcac96c88e7 (patch)
treefccc2ed8babd6c2c0b75651edf6d5d22e18dbd5c /python/qemu/utils/qemu_ga_client.py
parent9a3bf0e0ab628de7051b41a88c4628aa9e4d311b (diff)
downloadfocaccia-qemu-a2e3508ac0f2aeb27f859362bf8e6dcac96c88e7.tar.gz
focaccia-qemu-a2e3508ac0f2aeb27f859362bf8e6dcac96c88e7.zip
arm/cpu: Add sysreg definitions in cpu-sysregs.h
This new header contains macros that define aarch64 registers.
In a subsequent patch, this will be replaced by a more exhaustive
version that will be generated from linux arch/arm64/tools/sysreg
file. Those macros are sufficient to migrate the storage of those
ID regs from named fields in isar struct to an array cell.

[CH: reworked to use different structures]
[CH: moved accessors from the patches first using them to here,
     dropped interaction with writable registers, which will happen
     later]
[CH: use DEF magic suggested by rth]
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Sebastian Ott <sebott@redhat.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Message-id: 20250617153931.1330449-2-cohuck@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'python/qemu/utils/qemu_ga_client.py')
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