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authorMostafa Saleh <smostafa@google.com>2023-05-25 10:37:51 +0100
committerPeter Maydell <peter.maydell@linaro.org>2023-05-30 15:50:16 +0100
commitccc3ee38713381a823a6b9229b36a0a1b36d919d (patch)
tree4a5c962f6f039e3ee7d2f68862e784625037b42c /python/qemu/utils/qom.py
parent2eaeb7d593254a34f3e551865b687886c2698f96 (diff)
downloadfocaccia-qemu-ccc3ee38713381a823a6b9229b36a0a1b36d919d.tar.gz
focaccia-qemu-ccc3ee38713381a823a6b9229b36a0a1b36d919d.zip
hw/arm/smmuv3: Add CMDs related to stage-2
CMD_TLBI_S2_IPA: As S1+S2 is not enabled, for now this can be the
same as CMD_TLBI_NH_VAA.

CMD_TLBI_S12_VMALL: Added new function to invalidate TLB by VMID.

For stage-1 only commands, add a check to throw CERROR_ILL if used
when stage-1 is not supported.

Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Mostafa Saleh <smostafa@google.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20230516203327.2051088-9-smostafa@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'python/qemu/utils/qom.py')
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