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| author | Luc Michel <luc.michel@amd.com> | 2025-09-26 09:07:30 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-10-07 10:35:36 +0100 |
| commit | 1bec18fc13dce2f9a066fcb52b5d15b6d3141499 (patch) | |
| tree | 801aaf308abe6839ee1fac2a198ee9d3f0727a5b /python/qemu/utils | |
| parent | 6532bc7cc7f5560b7782a2799d9d5f0ac2719c42 (diff) | |
| download | focaccia-qemu-1bec18fc13dce2f9a066fcb52b5d15b6d3141499.tar.gz focaccia-qemu-1bec18fc13dce2f9a066fcb52b5d15b6d3141499.zip | |
hw/arm/xlnx-versal: VersalMap: add support for OR'ed IRQs
Improve the IRQ index in the VersalMap structure to turn it into a descriptor: - the lower 16 bits still represent the IRQ index - bit 18 is used to indicate a shared IRQ connected to a OR gate - bits 19 to 22 indicate the index on the OR gate. This allows to share an IRQ among multiple devices. An OR gate is created to connect the devices to the actual IRQ pin. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-13-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'python/qemu/utils')
0 files changed, 0 insertions, 0 deletions