diff options
| author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2023-09-12 10:24:04 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-10-12 11:29:31 +1000 |
| commit | 8ea3fceff4e0622f16441e261d125709c8819577 (patch) | |
| tree | ed8ad8626ecbddee599f62f257a0055eed228c73 /python/scripts/mkvenv.py | |
| parent | a51e5124a655b3dad80b36b18547cb1eca2c5eb2 (diff) | |
| download | focaccia-qemu-8ea3fceff4e0622f16441e261d125709c8819577.tar.gz focaccia-qemu-8ea3fceff4e0622f16441e261d125709c8819577.zip | |
target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
We'll add a new CPU type that will enable a considerable amount of extensions. To make it easier for us we'll do a few cleanups in our existing riscv_cpu_extensions[] array. Start by splitting all CPU non-boolean options from it. Create a new riscv_cpu_options[] array for them. Add all these properties in riscv_cpu_add_user_properties() as it is already being done today. 'mmu' and 'pmp' aren't really extensions in the usual way we think about RISC-V extensions. These are closer to CPU features/options, so move both to riscv_cpu_options[] too. In the near future we'll need to match all extensions with all entries in isa_edata_arr[], and so it happens that both 'mmu' and 'pmp' do not have a riscv,isa string (thus, no priv spec version restriction). This further emphasizes the point that these are more a CPU option than an extension. No functional changes made. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20230912132423.268494-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'python/scripts/mkvenv.py')
0 files changed, 0 insertions, 0 deletions