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| author | Mayuresh Chitale <mchitale@ventanamicro.com> | 2023-05-18 23:20:56 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-06-13 17:23:04 +1000 |
| commit | 9514fc72d0b92a973297fea0c82d64232a64d127 (patch) | |
| tree | 371d030cffdf26949f2230dc094061334bd01744 /python/scripts/vendor.py | |
| parent | 30a0d77622d105908e7d45cf34c73f781263ede5 (diff) | |
| download | focaccia-qemu-9514fc72d0b92a973297fea0c82d64232a64d127.tar.gz focaccia-qemu-9514fc72d0b92a973297fea0c82d64232a64d127.zip | |
target/riscv: smstateen check for fcsr
Implement the s/h/mstateen.fcsr bit as defined in the smstateen spec and check for it when accessing the fcsr register and its fields. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230518175058.2772506-2-mchitale@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'python/scripts/vendor.py')
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