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| author | Yong-Xuan Wang <yongxuan.wang@sifive.com> | 2024-05-15 17:11:28 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-06-03 11:12:12 +1000 |
| commit | 190b867f28cb5781f3cd01a3deb371e4211595b1 (patch) | |
| tree | 9e75dfea7765d06b72d0667434e8cd01dca53bd2 /python/scripts | |
| parent | c5eb8d6336741dbcb98efcc347f8265bf60bc9d1 (diff) | |
| download | focaccia-qemu-190b867f28cb5781f3cd01a3deb371e4211595b1.tar.gz focaccia-qemu-190b867f28cb5781f3cd01a3deb371e4211595b1.zip | |
target/riscv/kvm.c: Fix the hart bit setting of AIA
In AIA spec, each hart (or each hart within a group) has a unique hart number to locate the memory pages of interrupt files in the address space. The number of bits required to represent any hart number is equal to ceil(log2(hmax + 1)), where hmax is the largest hart number among groups. However, if the largest hart number among groups is a power of 2, QEMU will pass an inaccurate hart-index-bit setting to Linux. For example, when the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient to represent 4 harts, but we passes 3 to Linux. The code needs to be updated to ensure accurate hart-index-bit settings. Additionally, a Linux patch[1] is necessary to correctly recover the hart index when the guest OS has only 1 hart, where the hart-index-bit is 0. [1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/ Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Cc: qemu-stable <qemu-stable@nongnu.org> Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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