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| author | Anup Patel <anup.patel@wdc.com> | 2022-02-20 14:25:23 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-03-03 13:14:50 +1000 |
| commit | 9746e583fe6ca67d9645448989535bc19adb6150 (patch) | |
| tree | 1226b4e683e1e3f1a0c205d3077e3d3dc3c5b57f /python/tests/protocol.py | |
| parent | e6faee65855bf6d2ee480c5515f6d157c3229a38 (diff) | |
| download | focaccia-qemu-9746e583fe6ca67d9645448989535bc19adb6150.tar.gz focaccia-qemu-9746e583fe6ca67d9645448989535bc19adb6150.zip | |
hw/intc: Add RISC-V AIA IMSIC device emulation
The RISC-V AIA (Advanced Interrupt Architecture) defines a new interrupt controller for MSIs (message signal interrupts) called IMSIC (Incoming Message Signal Interrupt Controller). The IMSIC is per-HART device and also suppport virtualizaiton of MSIs using dedicated VS-level guest interrupt files. This patch adds device emulation for RISC-V AIA IMSIC which supports M-level, S-level, and VS-level MSIs. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-Id: <20220220085526.808674-3-anup@brainfault.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'python/tests/protocol.py')
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