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| author | Siarhei Volkau <lis8215@gmail.com> | 2023-06-08 13:41:53 +0300 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2023-07-10 23:33:38 +0200 |
| commit | 199fc7d2790ce07f054fc2773dce8ae9e9fc3046 (patch) | |
| tree | fca5fcf89c4f42e63e85f753fddca3d4f4087917 /python | |
| parent | 73c260c1a63cabe81676a28e957df10ea2395443 (diff) | |
| download | focaccia-qemu-199fc7d2790ce07f054fc2773dce8ae9e9fc3046.tar.gz focaccia-qemu-199fc7d2790ce07f054fc2773dce8ae9e9fc3046.zip | |
target/mips/mxu: Add S32MADD/MADDU/MSUB/MSUBU instructions
These instructions used to multiply 2x32-bit GPR sources & accumulate result into 64-bit pair of XRF registers. These instructions stain HI/LO registers with the final result. Their opcode is close to the MIPS32R1 MADD[U]/MSUB[U], so it have to call decode_opc_special2_legacy when failing to find MXU opcode. Moreover, it solves issue with reinventing MUL and malfunction MULU/CLZ/CLO instructions. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-5-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'python')
0 files changed, 0 insertions, 0 deletions