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| author | Luc Michel <luc.michel@amd.com> | 2025-09-26 09:07:21 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-10-07 10:35:36 +0100 |
| commit | 288dc87244c97c8674967c12bb5c8e38fd7d9ff5 (patch) | |
| tree | 842b45c007ced69e5adb493446a5b79f7babbb82 /python | |
| parent | d82be8c5de7a8bc1602b89678e69312c1716bd10 (diff) | |
| download | focaccia-qemu-288dc87244c97c8674967c12bb5c8e38fd7d9ff5.tar.gz focaccia-qemu-288dc87244c97c8674967c12bb5c8e38fd7d9ff5.zip | |
hw/arm/xlnx-versal: uart: refactor creation
Refactor the UARTs creations. The VersalMap struct is now used to describe the SoC and its peripherals. For now it contains the two UARTs mapping information. The creation function now embeds the FDT creation logic as well. The devices are now created dynamically using qdev_new and (qdev|sysbus)_realize_and_unref. This will allow to rely entirely on the VersalMap structure to create the SoC and allow easy addition of new SoCs of the same family (like versal2 coming with next commits). Note that the connection to the CRL is removed for now and will be re-added by next commits. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-4-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'python')
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