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| author | Frank Chang <frank.chang@sifive.com> | 2021-12-10 15:56:28 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-12-20 14:51:36 +1000 |
| commit | a75ae09f2a7ed09c017f22f04bf71bd7b453fef7 (patch) | |
| tree | 5d6b9bfd7d1b8bfe6ffd4e6c11b6a6bdfcbca384 /python | |
| parent | 8b99a110f7ff2c7e1d1294998226b84176384ef3 (diff) | |
| download | focaccia-qemu-a75ae09f2a7ed09c017f22f04bf71bd7b453fef7.tar.gz focaccia-qemu-a75ae09f2a7ed09c017f22f04bf71bd7b453fef7.zip | |
target/riscv: rvv-1.0: single-width bit shift instructions
Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211210075704.23951-43-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'python')
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