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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-10-21 15:58:42 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-11-02 14:32:32 +0100 |
| commit | ba7b6f025ba84a5a32c6cd07ffc8634ad2b33c20 (patch) | |
| tree | af8b53e18495bef5f37b65cb0aded5591c933a5f /python | |
| parent | 73053f62287256cb69e95f43fa424eb4342d6935 (diff) | |
| download | focaccia-qemu-ba7b6f025ba84a5a32c6cd07ffc8634ad2b33c20.tar.gz focaccia-qemu-ba7b6f025ba84a5a32c6cd07ffc8634ad2b33c20.zip | |
target/mips: Fix Loongson-3A4000 MSAIR config register
When using the Loongson-3A4000 CPU, the MSAIR is returned with a zero value (because unimplemented). Checking on real hardware, this value appears incorrect: $ cat /proc/cpuinfo system type : generic-loongson-machine machine : loongson,generic cpu model : Loongson-3 V0.4 FPU V0.1 model name : Loongson-3A R4 (Loongson-3A4000) @ 1800MHz isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2 ASEs implemented : vz msa loongson-mmi loongson-cam loongson-ext loongson-ext2 ... Checking the CFCMSA opcode result with gdb we get 0x60140: Breakpoint 1, 0x00000001200037c4 in main () 1: x/i $pc => 0x1200037c4 <main+52>: cfcmsa v0,msa_ir (gdb) si 0x00000001200037c8 in main () (gdb) i r v0 v0: 0x60140 MSAIR bits 17 and 18 are "reserved" per the spec revision 1.12, so mask them out, and set MSAIR=0x0140 for the Loongson-3A4000 CPU model added in commit af868995e1b. Cc: Huacai Chen <chenhuacai@kernel.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211026180920.1085516-1-f4bug@amsat.org>
Diffstat (limited to 'python')
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