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| author | Simon Burge <simonb@NetBSD.org> | 2021-12-14 00:51:27 +1100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2022-03-07 20:34:17 +0100 |
| commit | c8aeab3a09b51f828eaa50b994434dbfb3f626b8 (patch) | |
| tree | 5b1cd7d3464d76870f219f22a9048c27120af5ad /python | |
| parent | b49872aa8fc0f3f5a3036cc37aa2cb5c92866f33 (diff) | |
| download | focaccia-qemu-c8aeab3a09b51f828eaa50b994434dbfb3f626b8.tar.gz focaccia-qemu-c8aeab3a09b51f828eaa50b994434dbfb3f626b8.zip | |
target/mips: Fix cycle counter timing calculations
The cp0_count_ns value is calculated from the CP0_COUNT_RATE_DEFAULT constant in target/mips/cpu.c. The cycle counter resolution is defined per-CPU in target/mips/cpu-defs.c.inc; use this value for calculating cp0_count_ns. Fixings timing problems on guest OSs for the 20Kc CPU which has a CCRes of 1. Signed-off-by: Simon Burge <simonb@NetBSD.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211213135125.18378-1-simonb@NetBSD.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'python')
0 files changed, 0 insertions, 0 deletions