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authorAlexandre Mergnat <amergnat@baylibre.com>2020-07-06 10:45:50 +0200
committerAlistair Francis <alistair.francis@wdc.com>2020-07-13 17:25:37 -0700
commitcfad709bceb629a4ebeb5d8a3acd1871b9a6436b (patch)
treeecd23f58326ceec05471513539a5378ef980332b /python
parent895bfa84fec27899bf8e8c17f46358d31df2ab4f (diff)
downloadfocaccia-qemu-cfad709bceb629a4ebeb5d8a3acd1871b9a6436b.tar.gz
focaccia-qemu-cfad709bceb629a4ebeb5d8a3acd1871b9a6436b.zip
target/riscv: Fix pmp NA4 implementation
The end address calculation for NA4 mode is wrong because the address
used isn't shifted.

It doesn't watch 4 bytes but a huge range because the end address
calculation is wrong.

The solution is to use the shifted address calculated for start address
variable.

Modifications are tested on Zephyr OS userspace test suite which works
for other RISC-V boards (E31 and E34 core).

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200706084550.24117-1-amergnat@baylibre.com
Message-Id: <20200706084550.24117-1-amergnat@baylibre.com>
[ Changes by AF:
 - Improve the commit title and message
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'python')
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