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| author | Jiaxun Yang <jiaxun.yang@flygoat.com> | 2020-10-16 14:51:54 +0800 |
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| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-10-17 11:12:53 +0200 |
| commit | e10a0ca17dfeac25afb58f163b99d784b88d4e23 (patch) | |
| tree | f973f54c08bad83b058732b4ac5ac3ece743b55d /python | |
| parent | 32eb97b5eb24c1fc1a1c366f25e1ffe31f0e096a (diff) | |
| download | focaccia-qemu-e10a0ca17dfeac25afb58f163b99d784b88d4e23.tar.gz focaccia-qemu-e10a0ca17dfeac25afb58f163b99d784b88d4e23.zip | |
target/mips: Add loongson-ext lswc2 group of instructions (Part 1)
LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE as "load/store quad word" and "shifted load/store" groups of instructions. This patch add implementation of these instructions: gslq: load 16 bytes to GPR gssq: store 16 bytes from GPR gslqc1: load 16 bytes to FPR gssqc1: store 16 bytes from FPR Details of Loongson-EXT is here: https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhc@lemote.com> Message-Id: <1602831120-3377-3-git-send-email-chenhc@lemote.com> [PMD: Restrict t1 variable to TARGET_MIPS64, remove unused t2/fp0] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'python')
0 files changed, 0 insertions, 0 deletions