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| author | Peter Maydell <peter.maydell@linaro.org> | 2023-04-24 16:39:08 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-05-02 15:47:41 +0100 |
| commit | 7f3a3d3dc433dc06c0adb480729af80f9c8e3739 (patch) | |
| tree | 1c5b00076207196c8ee7d949a9522ebd91ea7111 /qga/commands-posix.c | |
| parent | 2c5fa0778c3b4307f9f3af7f27886c46d129c62f (diff) | |
| download | focaccia-qemu-7f3a3d3dc433dc06c0adb480729af80f9c8e3739.tar.gz focaccia-qemu-7f3a3d3dc433dc06c0adb480729af80f9c8e3739.zip | |
target/arm: Define and use new load_cpu_field_low32()
In several places in the 32-bit Arm translate.c, we try to use load_cpu_field() to load from a CPUARMState field into a TCGv_i32 where the field is actually 64-bit. This works on little-endian hosts, but gives the wrong half of the register on big-endian. Add a new load_cpu_field_low32() which loads the low 32 bits of a 64-bit field into a TCGv_i32. The new macro includes a compile-time check against accidentally using it on a field of the wrong size. Use it to fix the two places in the code where we were using load_cpu_field() on a 64-bit field. This fixes a bug where on big-endian hosts the guest would crash after executing an ERET instruction, and a more corner case one where some UNDEFs for attempted accesses to MSR banked registers from Secure EL1 might go to the wrong EL. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230424153909.1419369-2-peter.maydell@linaro.org
Diffstat (limited to 'qga/commands-posix.c')
0 files changed, 0 insertions, 0 deletions