diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2015-06-19 17:05:15 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-06-19 17:05:15 +0100 |
| commit | 799810fb2810ec4cb82f12ec9b023e1bfe434d71 (patch) | |
| tree | 6788be8c5ede10f11aefae993e88f494a634b22a /qobject/json-parser.c | |
| parent | ffdb1409a79c9cc91afd9f58df625fdca16bf8b9 (diff) | |
| parent | a59d31a1ebdce796a469242800db89bf09c94580 (diff) | |
| download | focaccia-qemu-799810fb2810ec4cb82f12ec9b023e1bfe434d71.tar.gz focaccia-qemu-799810fb2810ec4cb82f12ec9b023e1bfe434d71.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150619' into staging
target-arm queue: * support --semihosting-config,arg=value * Cortex-R5 support (including implementing them on the Zynq board) * Cortex-M4 support (without FPU) * enable vfio-calxeda-xgmac * don't reset ALIAS sysregs # gpg: Signature made Fri Jun 19 14:41:54 2015 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20150619: semihosting: add --semihosting-config arg sub-argument semihosting: create SemihostingConfig structure and semihost.h arm: xlnx-zynqmp: Add 2xCortexR5 CPUs arm: xlnx-zynqmp: Add boot-cpu property arm: xlnx-zynqmp: Preface CPU variables with "apu" target-arm: Add support for Cortex-R5 target-arm: Implement PMSAv7 MPU target-arm: Add registers for PMSAv7 target-arm/helper.c: define MPUIR register target-arm: Do not reset sysregs marked as ALIAS hw/arm/sysbus-fdt: enable vfio-calxeda-xgmac dynamic instantiation target-arm: Add the Cortex-M4 CPU Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'qobject/json-parser.c')
0 files changed, 0 insertions, 0 deletions