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| author | Peter Maydell <peter.maydell@linaro.org> | 2015-09-08 18:02:36 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-09-08 18:02:36 +0100 |
| commit | fc04a730b7e60f4a62d6260d4eb9c537d1d3643f (patch) | |
| tree | 71a0c298ca37f76a7467118aacbc8a38df0edd99 /qom/object.c | |
| parent | 8611280505119e296757a60711a881341603fa5a (diff) | |
| parent | 6fdf3282d16e7fb6e798824fb5f4f60c6a73067d (diff) | |
| download | focaccia-qemu-fc04a730b7e60f4a62d6260d4eb9c537d1d3643f.tar.gz focaccia-qemu-fc04a730b7e60f4a62d6260d4eb9c537d1d3643f.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150908' into staging
target-arm queue:
* Implement priority handling properly via GICC_APR
* Enable TZ extensions on the GIC if we're using them
* Minor preparatory patches for EL3 support
* cadence_gem: Correct Marvell PHY SPCFC reset value
* Support AHCI in ZynqMP
# gpg: Signature made Tue 08 Sep 2015 17:48:33 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
* remotes/pmaydell/tags/pull-target-arm-20150908:
xlnx-zynqmp: Connect the sysbus AHCI to ZynqMP
xlnx-zynqmp.c: Convert some of the error_propagate() calls to error_abort
ahci.c: Don't assume AHCIState's parent is AHCIPCIState
ahci: Separate the AHCI state structure into the header
cadence_gem: Correct Marvell PHY SPCFC reset value
target-arm: Add AArch64 access to PAR_EL1
target-arm: Correct opc1 for AT_S12Exx
target-arm: Log the target EL when taking exceptions
target-arm: Fix default_exception_el() function for the case when EL3 is not supported
hw/arm/virt: Enable TZ extensions on the GIC if we are using them
hw/arm/virt: Default to not providing TrustZone support
hw/cpu/{a15mpcore, a9mpcore}: enable TrustZone in GIC if it is enabled in CPUs
hw/intc/arm_gic_common: Configure IRQs as NS if doing direct NS kernel boot
hw/arm: new interface for devices which need to behave differently for kernel boot
qom: Add recursive version of object_child_for_each
hw/intc/arm_gic: Actually set the active bits for active interrupts
hw/intc/arm_gic: Drop running_irq and last_active arrays
hw/intc/arm_gic: Fix handling of GICC_APR<n>, GICC_NSAPR<n> registers
hw/intc/arm_gic: Running priority is group priority, not full priority
armv7m_nvic: Implement ICSR without using internal GIC state
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'qom/object.c')
| -rw-r--r-- | qom/object.c | 25 |
1 files changed, 22 insertions, 3 deletions
diff --git a/qom/object.c b/qom/object.c index eea8edf3d3..b7b05d3ffb 100644 --- a/qom/object.c +++ b/qom/object.c @@ -775,23 +775,42 @@ void object_class_foreach(void (*fn)(ObjectClass *klass, void *opaque), enumerating_types = false; } -int object_child_foreach(Object *obj, int (*fn)(Object *child, void *opaque), - void *opaque) +static int do_object_child_foreach(Object *obj, + int (*fn)(Object *child, void *opaque), + void *opaque, bool recurse) { ObjectProperty *prop, *next; int ret = 0; QTAILQ_FOREACH_SAFE(prop, &obj->properties, node, next) { if (object_property_is_child(prop)) { - ret = fn(prop->opaque, opaque); + Object *child = prop->opaque; + + ret = fn(child, opaque); if (ret != 0) { break; } + if (recurse) { + do_object_child_foreach(child, fn, opaque, true); + } } } return ret; } +int object_child_foreach(Object *obj, int (*fn)(Object *child, void *opaque), + void *opaque) +{ + return do_object_child_foreach(obj, fn, opaque, false); +} + +int object_child_foreach_recursive(Object *obj, + int (*fn)(Object *child, void *opaque), + void *opaque) +{ + return do_object_child_foreach(obj, fn, opaque, true); +} + static void object_class_get_list_tramp(ObjectClass *klass, void *opaque) { GSList **list = opaque; |