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| author | Nutty Liu <liujingqi@lanxincomputing.com> | 2025-06-05 20:48:48 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-07-04 21:09:48 +1000 |
| commit | 5000ba0cb1c513283f0a2f2f9742cfe8053dab8d (patch) | |
| tree | 8d0bea17c9038799c4feccc8fcb18cc63b7feebf /rust/qemu-api-macros/src/bits.rs | |
| parent | cd633bea8b0d30f3418b0dd372116bf3e028e42f (diff) | |
| download | focaccia-qemu-5000ba0cb1c513283f0a2f2f9742cfe8053dab8d.tar.gz focaccia-qemu-5000ba0cb1c513283f0a2f2f9742cfe8053dab8d.zip | |
hw/riscv/riscv-iommu: Fix PPN field of Translation-reponse register
The original implementation incorrectly performed a bitwise AND operation between the PPN of iova and PPN Mask, leading to an incorrect PPN field in Translation-reponse register. The PPN of iova should be set entirely in the PPN field of Translation-reponse register. Also remove the code that was used to clear S field since this field is already zero. Signed-off-by: Nutty Liu <liujingqi@lanxincomputing.com> Reviewed-by: Tomasz Jeznach <tjeznach@rivosinc.com> Message-ID: <20250605124848.1248-1-liujingqi@lanxincomputing.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'rust/qemu-api-macros/src/bits.rs')
0 files changed, 0 insertions, 0 deletions