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authorAndrew Jones <ajones@ventanamicro.com>2025-09-04 08:27:24 -0500
committerAlistair Francis <alistair.francis@wdc.com>2025-10-02 15:08:36 +1000
commit4f7528295b3e6dfe1189f660fa7865ad972d82e7 (patch)
treedc6a702c5095d3570608e3c5ec53291be042e192 /rust/qemu-api-macros/src
parent29b77c1a2db2d796bc3847852a5c8dc2a1e6e83b (diff)
downloadfocaccia-qemu-4f7528295b3e6dfe1189f660fa7865ad972d82e7.tar.gz
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hw/riscv/riscv-iommu: Fix MSI table size limit
The MSI table is not limited to 4k. The only constraint the table has
is that its base address must be aligned to its size, ensuring no
offsets of the table size will overrun when added to the base address
(see "8.5. MSI page tables" of the AIA spec).

Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation")
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20250904132723.614507-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'rust/qemu-api-macros/src')
0 files changed, 0 insertions, 0 deletions