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| author | Jamin Lin <jamin_lin@aspeedtech.com> | 2025-03-07 11:59:29 +0800 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2025-03-09 14:36:53 +0100 |
| commit | cd99eda62a5129305d186468f8056618d0b3bd87 (patch) | |
| tree | e8daf00f9cad449bf4f649ec3e86c78caec7eb07 /rust/qemu-api-macros | |
| parent | d2c8093567b3681e4439702f129e89156f59afb5 (diff) | |
| download | focaccia-qemu-cd99eda62a5129305d186468f8056618d0b3bd87.tar.gz focaccia-qemu-cd99eda62a5129305d186468f8056618d0b3bd87.zip | |
hw/arm/aspeed_ast27x0: Define an Array of AspeedINTCState with Two Instances
Updated Aspeed27x0SoCState to include an intc[2] array instead of a single AspeedINTCState instance. Modified aspeed_soc_ast2700_get_irq and aspeed_soc_ast2700_get_irq_index to correctly reference the corresponding interrupt controller instance and OR gate index. Currently, only GIC 192 to 201 are supported, and their source interrupts are from INTCIO and connected to INTC at input pin 0 and output pins 0 to 9 for GIC 192-201. To support both AST2700 A1 and A0, INTC input pins 1 to 9 and output pins 10 to 18 remain to support GIC 128-136, which source interrupts from INTC. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-21-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'rust/qemu-api-macros')
0 files changed, 0 insertions, 0 deletions