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| author | Rajnesh Kanwal <rkanwal@rivosinc.com> | 2025-02-05 11:18:47 +0000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-03-04 15:42:54 +1000 |
| commit | c48bd18eaeb676a7236030eb9b7984b9244d7750 (patch) | |
| tree | 896eb38a23c45d54d05c544d7a728717ed06b522 /rust/qemu-api/src/bitops.rs | |
| parent | 3f833f8920d815caa6cd0215a5707a03426ba574 (diff) | |
| download | focaccia-qemu-c48bd18eaeb676a7236030eb9b7984b9244d7750.tar.gz focaccia-qemu-c48bd18eaeb676a7236030eb9b7984b9244d7750.zip | |
target/riscv: Add support for Control Transfer Records extension CSRs.
This commit adds support for [m|s|vs]ctrcontrol, sctrstatus and sctrdepth CSRs handling. Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250205-b4-ctr_upstream_v6-v6-3-439d8e06c8ef@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'rust/qemu-api/src/bitops.rs')
0 files changed, 0 insertions, 0 deletions