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| author | Vasilis Liaskovitis <vliaskovitis@suse.com> | 2025-01-16 17:10:07 +0100 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-03-04 15:42:54 +1000 |
| commit | f73456781bf10a96849e2929488634f61eec8c5c (patch) | |
| tree | 2edcc3d606caaa427dbb0c70e845c919d6927a8b /rust/qemu-api/src/bitops.rs | |
| parent | 3521f9cadc29c7d68b73b325ddb46a7acebf6212 (diff) | |
| download | focaccia-qemu-f73456781bf10a96849e2929488634f61eec8c5c.tar.gz focaccia-qemu-f73456781bf10a96849e2929488634f61eec8c5c.zip | |
hw/riscv/virt: Add serial alias in DTB
Add an "aliases" node with a "serial0" entry for the single UART in the riscv virt machine. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2774 Signed-off-by: Vasilis Liaskovitis <vliaskovitis@suse.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250116161007.39710-1-vliaskovitis@suse.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'rust/qemu-api/src/bitops.rs')
0 files changed, 0 insertions, 0 deletions