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| author | Peter Maydell <peter.maydell@linaro.org> | 2025-03-12 13:25:07 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-03-14 12:54:33 +0000 |
| commit | 39ec3fc030166c594a64d1d197e29fa9d100d4c5 (patch) | |
| tree | 3236b1e99eb55326481b765a16b5417fc188fe2e /rust/qemu-api/src/c_str.rs | |
| parent | 5d71c6820f3b91763b5807311969cc0362d457d9 (diff) | |
| download | focaccia-qemu-39ec3fc030166c594a64d1d197e29fa9d100d4c5.tar.gz focaccia-qemu-39ec3fc030166c594a64d1d197e29fa9d100d4c5.zip | |
target/arm: HCR_EL2.RW should be RAO/WI if EL1 doesn't support AArch32
When EL1 doesn't support AArch32, the HCR_EL2.RW bit is supposed to be RAO/WI. Enforce the RAO/WI behaviour. Note that we handle "reset value should honour RES1 bits" in the same way that SCR_EL3 does, via a reset function. We do already have some CPU types which don't implement AArch32 above EL0, so this is technically a bug; it doesn't seem worth backporting to stable because no sensible guest code will be deliberately attempting to set the RW bit to a value corresponding to an unimplemented execution state and then checking that we did the right thing. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'rust/qemu-api/src/c_str.rs')
0 files changed, 0 insertions, 0 deletions