diff options
| author | Roman Artemev <roman.artemev@syntacore.com> | 2024-12-11 07:40:04 +0000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2024-12-12 14:28:38 -0600 |
| commit | b438362a142527b97b638b7f0f35ebe11911a8d5 (patch) | |
| tree | b4cf64f0abed9cdc4c59e114d871052946bf69e8 /rust/qemu-api/src/irq.rs | |
| parent | 04e006ab36a8565b92d4e21dd346367fbade7d74 (diff) | |
| download | focaccia-qemu-b438362a142527b97b638b7f0f35ebe11911a8d5.tar.gz focaccia-qemu-b438362a142527b97b638b7f0f35ebe11911a8d5.zip | |
tcg/riscv: Fix StoreStore barrier generation
On RISC-V to StoreStore barrier corresponds
`fence w, w` not `fence r, r`
Cc: qemu-stable@nongnu.org
Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com>
Signed-off-by: Roman Artemev <roman.artemev@syntacore.com>
Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'rust/qemu-api/src/irq.rs')
0 files changed, 0 insertions, 0 deletions