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| author | Richard Henderson <richard.henderson@linaro.org> | 2025-01-14 23:08:24 -0800 |
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| committer | Richard Henderson <richard.henderson@linaro.org> | 2025-04-28 13:40:17 -0700 |
| commit | e2f5ee36afb3b5306c99f40044534ae7d2580114 (patch) | |
| tree | bbed6a6e8bb0c06d934aee0422248c29b2404bf3 /rust/qemu-api/src/module.rs | |
| parent | aeb3514bd06b278dd026c90e8f71ca5b32762ab9 (diff) | |
| download | focaccia-qemu-e2f5ee36afb3b5306c99f40044534ae7d2580114.tar.gz focaccia-qemu-e2f5ee36afb3b5306c99f40044534ae7d2580114.zip | |
tcg/optimize: With two const operands, prefer 0 in arg1
For most binary operands, two const operands fold. However, the add/sub carry opcodes have a third input. Prefer "reg, zero, const" since many risc hosts have a zero register that can fit a "reg, reg, const" insn format. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'rust/qemu-api/src/module.rs')
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