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| author | Clément Léger <cleger@rivosinc.com> | 2025-01-16 14:15:36 +0100 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-01-19 09:44:35 +1000 |
| commit | 2d8e8259287ced7c689a7c7fad67ad2a417e477c (patch) | |
| tree | d415d0bdef0bd4899ed8b6dce6ddd637a7f63b47 /rust/qemu-api/src/qdev.rs | |
| parent | 00af7d53601b70f1353dabd1c87ffa260aafd27e (diff) | |
| download | focaccia-qemu-2d8e8259287ced7c689a7c7fad67ad2a417e477c.tar.gz focaccia-qemu-2d8e8259287ced7c689a7c7fad67ad2a417e477c.zip | |
target/riscv: Add Smdbltrp ISA extension enable switch
Add the switch to enable the Smdbltrp ISA extension and disable it for the max cpu. Indeed, OpenSBI when Smdbltrp is present, M-mode double trap is enabled by default and MSTATUS.MDT needs to be cleared to avoid taking a double trap. OpenSBI does not currently support it so disable it for the max cpu to avoid breaking regression tests. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250116131539.2475785-1-cleger@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'rust/qemu-api/src/qdev.rs')
0 files changed, 0 insertions, 0 deletions