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| author | Rajnesh Kanwal <rkanwal@rivosinc.com> | 2025-02-05 11:18:46 +0000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-03-04 15:42:54 +1000 |
| commit | 3f833f8920d815caa6cd0215a5707a03426ba574 (patch) | |
| tree | ce7ebeb969402dc6a301cf38aea1d68f906dff9a /rust/qemu-api/src | |
| parent | b638f679fede4835474a16cd423cb7e77ff6e7cc (diff) | |
| download | focaccia-qemu-3f833f8920d815caa6cd0215a5707a03426ba574.tar.gz focaccia-qemu-3f833f8920d815caa6cd0215a5707a03426ba574.zip | |
target/riscv: Add Control Transfer Records CSR definitions.
The Control Transfer Records (CTR) extension provides a method to record a limited branch history in register-accessible internal chip storage. This extension is similar to Arch LBR in x86 and BRBE in ARM. The Extension has been stable and the latest release can be found here https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0_rc5 Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250205-b4-ctr_upstream_v6-v6-2-439d8e06c8ef@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'rust/qemu-api/src')
0 files changed, 0 insertions, 0 deletions