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| author | Zhao Liu <zhao1.liu@intel.com> | 2025-07-11 18:21:27 +0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2025-07-12 15:28:21 +0200 |
| commit | 67d54014afcfdd316a0e9c979a0ff8145d4cf963 (patch) | |
| tree | 4849f5e1631974d2639d8a735fb41ec9d0b377a6 /rust/qemu-api/src | |
| parent | 1034b94fe98da35857f261d4db89ce2ebed8c5c3 (diff) | |
| download | focaccia-qemu-67d54014afcfdd316a0e9c979a0ff8145d4cf963.tar.gz focaccia-qemu-67d54014afcfdd316a0e9c979a0ff8145d4cf963.zip | |
i386/cpu: Add descriptor 0x49 for CPUID 0x2 encoding
The legacy_l2_cache (2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size) corresponds to descriptor 0x49, but at present cpuid2_cache_descriptors doesn't support descriptor 0x49 because it has multiple meanings. The 0x49 is necessary when CPUID 0x2 and 0x4 leaves have the consistent cache model, and use legacy_l2_cache as the default L2 cache. Therefore, add descriptor 0x49 to represent general L2 cache. Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Tested-by: Yi Lai <yi1.lai@intel.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250711102143.1622339-3-zhao1.liu@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'rust/qemu-api/src')
0 files changed, 0 insertions, 0 deletions