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| author | Jamin Lin <jamin_lin@aspeedtech.com> | 2025-05-15 16:09:44 +0800 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2025-05-25 23:39:11 +0200 |
| commit | 89d2a9f3f7564c9421d61153bbf7e24af95d34ee (patch) | |
| tree | 4b5ae995e97104df2c2a6121e02a82033a3e0ede /rust/qemu-api/src | |
| parent | 7b4e588000699701f5906746d1b5b845391705e6 (diff) | |
| download | focaccia-qemu-89d2a9f3f7564c9421d61153bbf7e24af95d34ee.tar.gz focaccia-qemu-89d2a9f3f7564c9421d61153bbf7e24af95d34ee.zip | |
hw/misc/aspeed_hace: Move register size to instance class and dynamically allocate regs
Dynamically allocate the register array by removing the hardcoded ASPEED_HACE_NR_REGS macro. To support different register sizes across SoC variants, introduce a new "nr_regs" class attribute and replace the static "regs" array with dynamically allocated memory. Add a new "aspeed_hace_unrealize" function to properly free the allocated "regs" memory during device cleanup. Remove the bounds checking in the MMIO read/write handlers since the MemoryRegion size now matches the (register array size << 2). This commit updates the VMState fields accordingly. The VMState version was already bumped in a previous patch of this series, so no further version change is needed. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250515081008.583578-13-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'rust/qemu-api/src')
0 files changed, 0 insertions, 0 deletions