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| author | Atish Patra <atishp@rivosinc.com> | 2025-01-10 00:21:31 -0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-01-19 09:44:35 +1000 |
| commit | dbcb6e1ccf3f25292a8700bb18997a4411fad82f (patch) | |
| tree | 8cbf23f56ed236e87afee5b1aa0663eb554300eb /rust/qemu-api/src | |
| parent | dc0280723dfc64d90e94155985853691d5ab9276 (diff) | |
| download | focaccia-qemu-dbcb6e1ccf3f25292a8700bb18997a4411fad82f.tar.gz focaccia-qemu-dbcb6e1ccf3f25292a8700bb18997a4411fad82f.zip | |
target/riscv: Enable S*stateen bits for AIA
As per the ratified AIA spec v1.0, three stateen bits control AIA CSR access. Bit 60 controls the indirect CSRs Bit 59 controls the most AIA CSR state Bit 58 controls the IMSIC state such as stopei and vstopei Enable the corresponding bits in [m|h]stateen and enable corresponding checks in the CSR accessor functions. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-ID: <20250110-counter_delegation-v5-3-e83d797ae294@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'rust/qemu-api/src')
0 files changed, 0 insertions, 0 deletions