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| author | Tommy Wu <tommy.wu@sifive.com> | 2025-01-06 13:43:35 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-01-19 09:44:35 +1000 |
| commit | f9653d4eb2ccaf6fe140e38fb1027a9e829d4062 (patch) | |
| tree | 0334a53d63443aa28974969eccf5b3bd510dc392 /rust/qemu-api/src | |
| parent | 3157a553ec6b9a52ad0aa6b52cca27d3a964167e (diff) | |
| download | focaccia-qemu-f9653d4eb2ccaf6fe140e38fb1027a9e829d4062.tar.gz focaccia-qemu-f9653d4eb2ccaf6fe140e38fb1027a9e829d4062.zip | |
target/riscv: Add Smrnmi cpu extension
This adds the properties for ISA extension Smrnmi. Also, when Smrnmi is present, the firmware (e.g., OpenSBI) must set mnstatus.NMIE to 1 before enabling any interrupts. Otherwise, all interrupts will be disabled. Since our current OpenSBI does not support Smrnmi yet, let's disable Smrnmi for the 'max' type CPU for now. We can re-enable it once OpenSBI includes proper support for it. Signed-off-by: Frank Chang <frank.chang@sifive.com> Signed-off-by: Tommy Wu <tommy.wu@sifive.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250106054336.1878291-6-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'rust/qemu-api/src')
0 files changed, 0 insertions, 0 deletions