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| author | Michael Clark <mjc@sifive.com> | 2019-01-04 23:24:04 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-01-09 10:00:52 -0800 |
| commit | 71877e29696b10b6cf69faa1009dd0ec3202741e (patch) | |
| tree | 631189c62c23c6a3f9a4c331ee36a780066a6c81 /scripts/analyse-locks-simpletrace.py | |
| parent | c7b951718815694284501ed01fec7acb8654db7b (diff) | |
| download | focaccia-qemu-71877e29696b10b6cf69faa1009dd0ec3202741e.tar.gz focaccia-qemu-71877e29696b10b6cf69faa1009dd0ec3202741e.zip | |
RISC-V: Implement atomic mip/sip CSR updates
Use the new CSR read/modify/write interface to implement atomic updates to mip/sip. Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'scripts/analyse-locks-simpletrace.py')
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