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| author | luporl <leandro.lupori@gmail.com> | 2018-06-08 11:46:55 +0200 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2018-06-12 10:44:36 +1000 |
| commit | bfda32a87bc77b9fac83f6c2789d65585115970d (patch) | |
| tree | d0c3d91e63c01c871f9d34861d41cb035d35f304 /scripts/argparse.py | |
| parent | 42a907e83921ff2c4f5e6ca9fa6aa6791b43a73f (diff) | |
| download | focaccia-qemu-bfda32a87bc77b9fac83f6c2789d65585115970d.tar.gz focaccia-qemu-bfda32a87bc77b9fac83f6c2789d65585115970d.zip | |
target/ppc: Allow PIR read in privileged mode
According to PowerISA, the PIR register should be readable in privileged mode also, not only in hypervisor privileged mode. PowerISA 3.0 - 4.3.3 Processor Identification Register "Read access to the PIR is privileged; write access is not provided." Figure 18 in section 4.4.4 explicitly confirms that mfspr PIR is privileged and doesn't require hypervisor state. Cc: David Gibson <david@gibson.dropbear.id.au> Cc: Alexander Graf <agraf@suse.de> Cc: qemu-ppc@nongnu.org Signed-off-by: Leandro Lupori <leandro.lupori@gmail.com> Reviewed-by: Jose Ricardo Ziviani <joserz@linux.ibm.com> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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