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| author | Luc Michel <luc.michel@amd.com> | 2025-09-26 09:07:34 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-10-07 10:35:36 +0100 |
| commit | 176faad4bf7565966398df0d6e8cd05825dfceea (patch) | |
| tree | 913c444cfa13f1e44c30c932416c4a9b190f9ec5 /scripts/arm_processor_error.py | |
| parent | 060b809271f9d0d6205fe2232d0aead4a37fa0e7 (diff) | |
| download | focaccia-qemu-176faad4bf7565966398df0d6e8cd05825dfceea.tar.gz focaccia-qemu-176faad4bf7565966398df0d6e8cd05825dfceea.zip | |
hw/arm/xlnx-versal: rtc: refactor creation
Refactor the RTC device creation using the VersalMap structure. The sysbus IRQ output 0 (APB IRQ) is connected instead of the output 1 (addr error IRQ). This does not change the current behaviour since the RTC model does not implement those IRQs anyway. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-17-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'scripts/arm_processor_error.py')
0 files changed, 0 insertions, 0 deletions