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| author | Jean-Philippe Brucker <jean-philippe@linaro.org> | 2023-11-10 09:05:58 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-11-13 13:13:49 +0000 |
| commit | 1d675e59ea194fc918fe0f553eb79209b3fb3a8f (patch) | |
| tree | 9c8ab64459e5460b7badca29e6dc1b6fbaed682e /scripts/block-coroutine-wrapper.py | |
| parent | 69680740eafa1838527c90155a7432d51b8ff203 (diff) | |
| download | focaccia-qemu-1d675e59ea194fc918fe0f553eb79209b3fb3a8f.tar.gz focaccia-qemu-1d675e59ea194fc918fe0f553eb79209b3fb3a8f.zip | |
hw/arm/virt: fix GIC maintenance IRQ registration
Since commit 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic"),
GIC maintenance IRQ registration fails on arm64:
[ 0.979743] kvm [1]: Cannot register interrupt 9
That commit re-defined VIRTUAL_PMU_IRQ to be a INTID but missed a case
where the maintenance IRQ is actually referred by its PPI index. Just
like commit fa68ecb330db ("hw/arm/virt: fix PMU IRQ registration"), use
INITID_TO_PPI(). A search of "GIC_FDT_IRQ_TYPE_PPI" indicates that there
shouldn't be more similar issues.
Fixes: 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic")
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20231110090557.3219206-2-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'scripts/block-coroutine-wrapper.py')
0 files changed, 0 insertions, 0 deletions