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authorPeter Maydell <peter.maydell@linaro.org>2020-09-10 18:38:54 +0100
committerPeter Maydell <peter.maydell@linaro.org>2020-10-01 15:31:00 +0100
commit51cb228a1d1c0e325b4e7dea0bfb3140d6d11422 (patch)
tree8e4ce18682c9447df73be04a2e2b5104a7b96f38 /scripts/check_sparse.py
parentd20c3ebda2972255e67c0a07368ac37f37a16c04 (diff)
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target/arm: Add ID register values for Cortex-M0
Give the Cortex-M0 ID register values corresponding to its
implemented behaviour.  These will not be guest-visible but will be
used to govern the behaviour of QEMU's emulation.  We use the same
values that the Cortex-M3 does.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200910173855.4068-5-peter.maydell@linaro.org
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