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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-11-01 16:08:14 +0000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-11-02 14:14:55 -0400 |
| commit | dbd9e08476f09cf3556b9b8a306bf277172841a9 (patch) | |
| tree | bbf2e9e9627b6b33a9d4d6a731e8027559891b75 /scripts/meson-buildoptions.py | |
| parent | da2f02b360f405d7badc4a3028276e07db58026c (diff) | |
| download | focaccia-qemu-dbd9e08476f09cf3556b9b8a306bf277172841a9.tar.gz focaccia-qemu-dbd9e08476f09cf3556b9b8a306bf277172841a9.zip | |
target/arm: Advertise MVE to gdb when present
Cortex-M CPUs with MVE should advertise this fact to gdb, using the org.gnu.gdb.arm.m-profile-mve XML feature, which defines the VPR register. Presence of this feature also tells gdb to create pseudo-registers Q0..Q7, so we do not need to tell gdb about them separately. Note that unless you have a very recent GDB that includes this fix: http://patches-tcwg.linaro.org/patch/58133/ gdb will mis-print the individual fields of the VPR register as zero (but showing the whole thing as hex, eg with "print /x $vpr" will give the correct value). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20211101160814.5103-1-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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